#include <gpio.h>
__initdata int gpio_ss_table[][2] = {
	{32*1+7,	GSS_IGNORE  	        },	/* ISP_SDA */
	{32*1+8,	GSS_IGNORE  	        },	/* ISP_SCK */
	{32*1+20,	GSS_INPUT_NOPULL	},	/* MSC0_D0 */
	{32*1+21,	GSS_INPUT_NOPULL	},	/* MSC0_D1 */
	{32*1+28,	GSS_INPUT_NOPULL	},	/* MSC0_CLK */
	{32*1+29,	GSS_INPUT_NOPULL	},	/* MSC0_CMD */
	{32*1+30,	GSS_INPUT_NOPULL	},	/* MSC0_D2 */
	{32*1+31,	GSS_INPUT_NOPULL	},	/* MSC0_D3 */
	{32*2+2,	GSS_INPUT_PULL		},	/* LCD_D0 */
	{32*2+3,	GSS_INPUT_PULL		},	/* LCD_D1 */
	{32*2+4,	GSS_INPUT_PULL		},	/* LCD_D2 */
	{32*2+5,	GSS_INPUT_PULL		},	/* LCD_D3 */
	{32*2+6,	GSS_INPUT_PULL		},	/* LCD_D4 */
	{32*2+7,	GSS_INPUT_PULL		},	/* LCD_D5 */
	{32*2+8,	GSS_INPUT_PULL		},	/* LCD_D6 */
	{32*2+9,	GSS_INPUT_PULL		},	/* LCD_D7 */
	{32*2+12,	GSS_INPUT_PULL		},	/* LCD_RD */
	{32*2+13,	GSS_INPUT_PULL		},	/* LCD_CS */
	{32*2+14,	GSS_OUTPUT_LOW		},	/* LCD_RESET */
	{32*2+15,	GSS_INPUT_PULL		},	/* SW1 */
	{32*2+16,	GSS_INPUT_PULL		},	/* SW2 */
	{32*2+17,	GSS_INPUT_PULL		},	/* SW3 */
	{32*2+22,	GSS_INPUT_PULL		},	/* SW4 */
	{32*2+23,	GSS_INPUT_PULL		},	/* SW5 */
	{32*2+24,	GSS_INPUT_PULL		},	/* SW6 */
	{32*2+25,	GSS_INPUT_PULL		},	/* LCD_WR */
	{32*2+26,	GSS_INPUT_PULL		},	/* LCD_RS */
	{32*2+27,	GSS_INPUT_PULL		},	/* LCD_TE */
	{32*3+0,	GSS_INPUT_PULL  	},	/* PMU_IRQ_N */
	{32*3+1,	GSS_INPUT_NOPULL	},	/* SLEEP */
	{32*3+2,	GSS_IGNORE      	},	/* WL_WAKE_HOST */
	{32*3+3,	GSS_IGNORE	        },	/* AF_EN */
	{32*3+4,	GSS_IGNORE	        },	/* CIM_PWDN_N */
	{32*3+5,	GSS_INPUT_PULL      	},	/* USB_SEL */
	{32*3+6,	GSS_INPUT_PULL  	},	/* USB_DET */
	{32*3+7,	GSS_IGNORE       	},	/* CAMERA_LED */
	{32*3+8,	GSS_IGNORE      	},	/* HOST_WAKE_BT */
	{32*3+9,	GSS_IGNORE      	},	/* WL_REG_EN */
	{32*3+10,	GSS_IGNORE      	},	/* BT_REG_EN */
	{32*3+11,	GSS_IGNORE      	},	/* BT_WAKE_HOST */
	{32*3+12,	GSS_OUTPUT_LOW  	},	/* RECORDING_LED */
	{32*3+14,	GSS_INPUT_NOPULL	},	/* CLK32K */
	{32*3+17,	GSS_INPUT_PULL		},	/* BOOT_SEL0 */
	{32*3+18,	GSS_INPUT_NOPULL	},	/* BOOT_SEL1 */
	{32*3+19,	GSS_INPUT_PULL		},	/* BOOT_SEL2 */
	{32*3+26,	GSS_IGNORE		},	/* UART1_TXD */
	{32*3+27,	GSS_INPUT_PULL		},	/* SDXC_SW */
	{32*3+28,	GSS_INPUT_PULL      	},	/* SD_CD_N */
	{32*3+29,	GSS_IGNORE		},	/* UART1_RXD */
	{32*3+30,	GSS_IGNORE      	},	/* GPIO0 */
	{32*3+31,	GSS_IGNORE      	},	/* GPIO1 */
	{32*4+0,	GSS_IGNORE      	},	/* GPIO2 */
	{32*4+1,	GSS_OUTPUT_LOW  	},	/* LCD_PWM */
	{32*4+2,	GSS_IGNORE	        },	/* CIM_MCLK */
	{32*4+3,	GSS_IGNORE      	},	/* GPIO3 */
	{32*4+10,	GSS_OUTPUT_LOW		},	/* DRVVBUS */
	{32*4+20,	GSS_IGNORE		},	/* SDIO_D0_WIFI */
	{32*4+21,	GSS_IGNORE		},	/* SDIO_D1_WIFI */
	{32*4+22,	GSS_IGNORE		},	/* SDIO_D2_WIFI */
	{32*4+23,	GSS_IGNORE		},	/* SDIO_D3_WIFI */
	{32*4+28,	GSS_IGNORE		},	/* SDIO_CLK_WIFI */
	{32*4+29,	GSS_IGNORE		},	/* SDIO_CMD_WIFI */
	{32*4+30,	GSS_INPUT_PULL       	},	/* SMB1_SDA */
	{32*4+31,	GSS_INPUT_PULL       	},	/* SMB1_CLK */
	{32*5+0,	GSS_IGNORE		},	/* BT_UART0_RXD */
	{32*5+1,	GSS_IGNORE		},	/* BT_UART0_CTS */
	{32*5+2,	GSS_IGNORE		},	/* BT_UART0_RTS */
	{32*5+3,	GSS_IGNORE		},	/* BT_UART0_TXD */
	{32*5+6,	GSS_IGNORE		},	/* DMIC_CLK */
	{32*5+7,	GSS_IGNORE		},	/* DMIC_DOUT */
	{32*5+12,	GSS_IGNORE		},	/* BT_PCM_DO */
	{32*5+13,	GSS_IGNORE		},	/* BT_PCM_CLK */
	{32*5+14,	GSS_IGNORE		},	/* BT_PCM_SYN */
	{32*5+15,	GSS_IGNORE		},	/* BT_PCM_DI */
	{GSS_TABLET_END	,GSS_TABLET_END	}
};
